The present invention relates broadly to CMOS-SOS integrated circuits, and in particular to a radiation-induced substrate photo-current compensation apparatus.
The state of the art of integrated circuit photo-current compensation circuits is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents:
U.S. Pat. No. 4,368,085 issued to Peel on Jan. 11, 1983;
U.S. Pat. No. 4,489,339 issued to Uchida on Dec. 18, 1984; and
U.S. Pat. No. 4,520,382 is issued to Shimura on May 28, 1985.
The Peel patent describes a silicon-on-sapphire semiconductor apparatus and the method of fabrication thereof. A silicon nitride layer is disposed over the upper edge of the silicon island, and acts to prevent gate oxide breakdown.
The Uchida patent relates to an SOS MOSFET with a self-aligned channel contact. This MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate.
The Shimura patent illustrates a monolithic semiconductor integrated circuit device suited for suppressing a leakage current ascribable to an inversion layer accompanied to MOS (Metal-oxide-Semiconductor) structure.
Silicon-on-sapphire (SOS) is an intrinsically radiation-hard semiconductor technology. Silicon-on-sapphire semiconductors have been the subject of research and development for a number of years. Silicon-on-sapphire integrated circuitry is presently the leading candidate for implementation in strategic equipment such as a missile which must operate/survive a peak-dose-rate radiation event. The performance requirements for new missile systems are quite severe. Thus, the search for new device physics/circuit approaches or techniques which can be applied to silicon-on-sapphire semiconductors to yield increased radiation hardness, i.e., total dose and especially transient performance, is an active and crucial task. This situation applies to a wide class of silicon-on-sapphire circuitry generally, but in specific areas the need is especially critical.
In a high-dose-rate radiation event, electron-hole pairs which are generated thereby, create transient photocurrents. Experimental evidence has shown that the total photocurrent in a silicon FET on a sapphire substrate is made up of two distinct components: (1) a primary photocurrent (I.sub.pp) which flows directly in the silicon semiconductor between the device source and drain, and (2) a substrate photocurrent (I.sub.ps) which flows in the substrate beneath, between, and around the source and drain. The experimental evidence is that the substrate photocurrent is the major component of the radiation induced photocurrent. Estimates for the ratio (I.sub.ps /I.sub.pp) range from a factor of 3-5 to as high as a factor of 10.
Failure vehicles or mechanisms for silicon-on-sapphire integrated circuits in a high-dose-rate ionizing radiation event are of two types: (1) a total dose failure due to threshold shift is always an issue and must be considered, and (2) a failure due to transient photocurrents which can destroy memory data integrity and render the circuit at least temporarily inoperative. In a peak-dose-rate event, this transient photocurrent failure mode would be the probable major failure mode. Since (I.sub.ps /I.sub.pp) is greater than one, the substrate photocurrent, I.sub.ps, is seen to be the major-failure-mode contributor.
In the present state-of-the-art for silicon-on-sapphire semiconductor circuit design, the primary photocurrent I.sub.pp which flows in the silicon is a consideration in device/circuit design. For example, FETs may be sized to reflect expected I.sub.pp s in a circuit. Thus there has been an attempt in the prior art to compensate for the silicon photocurrent I.sub.pp. However, there presently appears to be no circuit compensation techniques for the prompt gamma photocurrent I.sub.ps flowing in the substrate which have as yet been developed or employed. It is clear, however, that the electronic/electrical behavior of the sapphire substrate plays a key role in determining the performance of a silicon-on-sapphire semiconductor transistor or circuit in a peak-dose-rate ionizing radiation environment and the prior art/current practice is clearly deficient.